Monthly Archives: December 2013

Some words about “hardware accelerated” instructions.

Recent leaks[0][1] created a public debate about about agencies backdooring the new instruction RDRAND[2][3] used to return random numbers. I’ve no evidence of anybody backdooring RDRAND but if anyone did I’m still curious about *how*. That’s why I started wondering, about what would be the nicest way to backdoor an instruction then I remember about RDTSC[5] which is an instruction used to read Time Stamp Counter, sometimes used to get random numbers.

RDTSC / RDPMC

Operation: RDTSC
IF (CR4.TSD 0) OR ((CR4.TSD 1) AND (CPL=0))
THEN
EDX:EAX TimeStampCounter;
ELSE (* CR4 is 1 and CPL is 1, 2, or 3 *)
#GP(0)
FI;

It is possible to hijack RDTSC by making it a privileged instruction by modifying the TSD flag in CR4, this is a widely known trick[6] for several years now. Same thing is possible with the RDPMC[5.2] instruction, which was known as a “secret” opcode, by modifying the PCE flag in CR4.

Operation: RDPMC
IF (ECX 0 OR 1) AND ((CR4.PCE 1) OR ((CR4.PCE 0) AND (CPL=0)))
THEN
EDX:EAX PMC[ECX];
ELSE (* ECX is not 0 or 1 and/or CR4.PCE is 0 and CPL is 1, 2, or 3 *)
#GP(0); FI;

In both cases, modifying this flag generates a #GP(General Protection) fault each time the instruction is executed which which internally cause the #GP trap handler (nt!KiTrap0D on Windows) to be executed. So if an individual hooks KiTrap0D (which should be prevented by Microsoft Windows Kernel Intregity such as PatchGuard), it can also emulate each execution of RDTSC and its returned values.

Control Registers

There are 5 control registers available (CR0, CR1, CR2, CR3, CR4 and CR8) as per documented by section 2.5 CONTROL REGISTERS of Volume 3A:
System Programming Guide, Part 1. [9]

As you can see below, numerous entries had been added to CR4 and numeries bitfields are marked as “reserved” or are undocumented.
control_registers

22-31 UNUSED?
21 SMAP Supervisor Mode Access Protection Enable If set, access of data in a higher ring generates a fault
20 SMEP Supervisor Mode Execution Protection Enable If set, execution of code in a higher ring generates a fault
19 UNDOCUMENTED
18 OSXSAVE XSAVE and Processor Extended States Enable
17 PCIDE PCID Enable If set, enables process-context identifiers
16 FSGSBASE
15 UNDOCUMENTED
14 SMXE Safer Mode Extensions Enable See Trusted Execution Technology (TXT)
13 VMXE Virtual Machine Extensions Enable See Intel VT-x
12 UNDOCUMENTED
11 UNDOCUMENTED
10 OSXMMEXCPT Operating System Support for Unmasked SIMD Floating-Point Exceptions If set, enables unmasked SSE exceptions.

Since the introduction of Intel VT-x (~2005), more than 11 bitfields had been added and 4 remain undocumented on purpose, and 10 (22-31) are supposedly reserved but it’s are to tell how many of them are actually undocumented until the next release processor release.
Given the chronology of the added features, bitfields 15 and 19 of CR4 are potentially interesting. But again, it’s assuming CR4 is the only interesting register. There are actually so many other places that could be interesting, those are just the obvious ones.

New Instructions Set

With the introduction of Advanced Vector Extensions (AVX) by Intel since 2010[9], 2012[7] and 2013[8], we saw several new instructions being introduced in Intel processors such as RDRAND but also instructions entirely dedicated to cryptography such as AES [1] (AESENC, AESENCLAST, AESDEC, AESDECLAST, AESKEYGENASSIST, AESIMC, PCLMULQDQ) and SHA-1 [2] (SHA1NEXTE, SHA1RNDS4, SHA1MSG1, SHA1MSG2, SHA256RNDS4, SHA256MSG1 and SHA256MSG2).

It’s quiet interesting to see who use and who documented those new instructions online.

Some funny comments can be seen online such as the ones on TrueCrypt[4] website:

By default, TrueCrypt uses hardware-accelerated AES on computers that have a processor where the Intel AES-NI instructions are available. Specifically, TrueCrypt uses the AES-NI instructions that perform so-called AES rounds (i.e. the main portions of the AES algorithm).** TrueCrypt does not use any of the AES-NI instructions that perform key generation.

Few more words

Now the question to me is why should I trust any software using “hardware acceleration” for cryptography purposes. Especially now that people are more and more interested in hardware-based cryptography attacks[10] using techniques, as a security researcher, I’d not even imagine. Attacks and attackers are definitely becoming more and more sophisticated. Now I’m quiet curious to see what new things 2014 has for us.

[0] December 20, 2013 – Exclusive: Secret contract tied NSA and security industry pioneerhttp://www.reuters.com/article/2013/12/20/us-usa-security-rsa-idUSBRE9BJ1C220131220
[1] September 5, 2013 – N.S.A. Able to Foil Basic Safeguards of Privacy on Web http://www.nytimes.com/2013/09/06/us/nsa-foils-much-internet-encryption.html?pagewanted=all
[2] December 10, 2013 – ‘We cannot trust them anymore’: Engineers abandon encryption chips after Snowden leakshttp://rt.com/usa/snowden-leak-rng-randomness-019/
[3] 5 September 2013, ‘I am so glad I resisted pressure from Intel engineers to let /dev/random rely only on the RDRAND instruction.’https://plus.google.com/+TheodoreTso/posts/SDcoemc9V3J
[4] TrueCrypt – Hardware Accelerationhttp://www.truecrypt.org/docs/hardware-acceleration
[5] RDTSC – Read Time Stamp Counter – http://www.rz.uni-karlsruhe.de/rz/docs/VTune/reference/vc275.htm
[5.2] RDPMC – Read Performance-Monitoring Countershttp://www.rcollins.org/p6/opcodes/RDPMC.html
[6] May 2009, Time-stamp counter disabling oddities in the Linux kernelhttp://blog.cr0.org/2009/05/time-stamp-counter-disabling-oddities.html
[7] September 2012, Intel® Advanced Encryption Standard (AES) New Instructions Sethttp://download-software.intel.com/sites/default/files/article/165683/aes-wp-2012-09-22-v01.pdf
[8] July 2013, Intel® Architecture Instruction Set Extensions Programming Reference http://download-software.intel.com/sites/default/files/319433-015.pdf
[9] July 2010, New instructions http://www.semiaccurate.com/forums/showthread.php?t=2870
[10] December 2013, RSA Key Extraction via Low-Bandwidth Acoustic Cryptanalysis, http://www.cs.tau.ac.il/~tromer/acoustic/

Solution challenge Hacknowledge 2013


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Challenge downloadable here: http://www.moonsols.com/private/challenge_msuiche.zip
Source code available here: http://moonsols.com/private/challenge_msuiche.c

01

The goal of the challenge is to find the right password which is passed as an argument. The main challenge is to reverse the p-code engine to be able to understand what algorithm are being used. The password itself is a 9 characters string, the first 4 characters “L0ve” are hardcoded in the routine, and the last 5 characters “CrC32″ have to be brute-forced to be retrieved. The second part of the password uses a modified version of Crc32 and both routines are written as p-code.
If people want to learn more about how p-code works, the source code is available above.

To help with the reversing of p-code engine, I left a debug mode inside the executable as we can see in the screenshot below. This is by default disabled but is editable. Once this variable is enabled, the VM Context (_VM_CONTEXT) is displayed each time the instruction pointer is updated – this way the code become traceable without much effort.
02

  1. span class=”coMULTI”>/* Fixed size stack. Right before Rip *//* Rip is 4 bytes aligned. */

As I said above the password is divided in two parts, the first part is hard-coded and the second one is a modified Crc32.

Let’s first have a look at the hard-coded checks, which is done character by character.

  1. #if 1
  2.     //
  3.     // Magic prefix (L0ve)
  4.     //
  5. /* r04 = 0x000000ff */‘L’,          /* r05 = 4 *//* r06 = [r00] *//* r06 &= 0xff *//* cmp r00, r01 *//* if ([input_string_len] != ‘L’) return; *//* r00 += 1 *//* reg01 -= 1 */‘0’,          /* r05 = 4 *//* r06 = [r00] *//* r06 &= 0xff *//* cmp r00, r01 *//* if ([input_string_len] != ‘L’) return; *//* r00 += 1 *//* reg01 -= 1 */‘v’,          /* r05 = 4 *//* r06 = [r00] *//* r06 &= 0xff *//* cmp r00, r01 *//* if ([input_string_len] != ‘L’) return; *//* r00 += 1 *//* reg01 -= 1 */‘e’,          /* r05 = 4 *//* r06 = [r00] *//* r05 &= 0xff *//* cmp r00, r01 *//* if ([input_string_len] != ‘L’) return; *//* r00 += 1 *//* reg01 -= 1 */
  6. #endif

And now let’s have a look at the second part of the routine, as you can see it’s computing the modified Crc32 with 0xeb8ec53d value and if the comparison succeed – it will initialize the g_IsValid variable.

  1.    // crc32 = r03; (0xffffffff)
  2. /* r04 = 0x000000ff */
  3.     // for (i = 0; i < strlen(input); i+= 1)
  4. /* begin_block: */
  5.  
  6.     // crc32 = (crc32 >> 8) ^ Crc32Table[ (crc32 ^ byteBuf[i]) & 0xFF ];
  7. /* r05 =  r03 *//* r05 &= 0xff *//* r06 = [r00] *//* r06 &= 0xff *//* r05 ^= r06 *//* r06 = 8 *//* r03 >>= r06 *//* r06 = Crc32Table *//* r07 = 4 *//* r05 *= r07 *//* r06 += r05 *//* r06 = [r06] *//* r03 ^= r06 *//* r00 += 1 *//* reg01 -= 1 *//* jne previous_block *//* r00 = r03 *//* r03 = 0xFFFFFFFF */
  8.  
  9.     // crc32 ^= 0xFFFFFFFF
  10. /* r00 ^= r03 *//* r01 = 0xeb8ec53d (expected value) (Crc32Mod("CrC32")) *//* r01 ^= r00 *//* if (r01) return; *//* r00 = g_IsValid *//* r01 = 0xFFFFFFFF *//* [r00] = 1 */

That’s pretty much it, like I said the source code is available above if you want to learn more about the code itself. The source-code also contains a C version of the p-code routines that had been used for checks. If you have any questions don’t hesitate to contact me on Twitter at @msuiche.